1. Field of the Invention
The present invention generally relates to driver circuits and more particularly to improved pull-up and pull down boost circuitry for drivers that minimizes block delay skew.
2. Description of the Related Art
As technology advances, device sizes get smaller. Likewise, maximum operating voltages decrease with each new technology. With smaller device sizes and a lower VDD, it becomes very difficult to improve block delay and reduce di/dt while still maintaining appropriate slew rates and keeping the design within the specifications. This invention tightens the slew rate and also minimizes block delay skew and jitter across different PVT conditions.
The invention begins with a driver circuit that includes a logical enable device and a driving transistor. In order to tighten slew rate and minimize delay skew, the invention adds a pull-down booster circuit connected to the gate of the driving transistor and/or a pull-up booster circuit connected to the gate of the driving transistor. The pull-down booster circuit is adapted to kly start pulling down the voltage at the gate of the driving transistor when the voltage level at the input to the logical enable device changes from a first voltage (e.g., a logical xe2x80x9c0xe2x80x9d) to a second higher voltage (e.g., a logical xe2x80x9c1xe2x80x9d). The pull-down booster than dynamically shuts itself off when the voltage level at feedback node G (the gate of the driving transistor) changes from a first voltage (e.g., a logical 1) to a second lower voltage (e.g. a logical 0). The voltage level at feedback node G (the gate of the driving transistor) only needs to fall to a threshold voltage below the voltage supply to start shutting off the pull-down booster. Thus, the stronger the pull-down booster circuit is, the faster it will shut itself off. This is why the pull-down boost circuit can be considered dynamic and sensitive to different process, temperature and voltage conditions. After the pull-down booster shuts off, the voltage level at the gate of the driving transistor is controlled by the logical enable device which controls the slew rate and di/dt by utilizing resistors in series with the CMOS FETS. By using only the resistors to control di/dt and slew rates, the circuit is adversely affected in terms of delay. By using the boost circuit in combination with the resistors, the invention is able to get a balance of delay, slew rate control, reduced di/dt, and less overshoot/undershoot voltage at the PAD. The pull-up booster circuit is adapted to dynamically pull-up the voltage at the gate of the driving transistor when the voltage level at the input to the logical enable device changes in the opposite direction.
The pull-down booster circuit has a logical NAND device having one input connected to an input signal supplied to the logical enable device. The pull-down booster circuit also includes a pull-down transistor that has its gate connected to the output of the NAND device, a source connected to the output of the logical enable device (and the gate of the driving transistor), and a drain connected to ground. The second input of the logical NAND device is connected to the output of the logical enable device, such that the logical NAND device dynamically activates the pull-down transistor to pull-down the gate of the driving transistor to ground (e.g., a logical xe2x80x9c0xe2x80x9d) only while the input signal supplied to the logical enable device is at the second voltage level (e.g., a logical xe2x80x9c1xe2x80x9d) and the signal on the output of the logical enable device (and the gate of the driving transistor) is also at the second voltage level (e.g., a logical xe2x80x9c1xe2x80x9d).
The pull-up booster circuit has a logical NOR device having one input connected to the input signal supplied to the logical enable device. The pull-up booster circuit also includes a pull-up transistor that has its gate connected to an output of the NOR device, a drain connected to an output of the logical enable device (and the gate of the driving transistor), and a source connected to the higher voltage level. The second input of the logical NOR device is connected to the output of the logical enable device (and the gate of the driving transistor), such that the logical NOR device activates the pull-up transistor to pull-up the gate of the driving transistor to the higher voltage level (e.g., a logical xe2x80x9c1xe2x80x9d) only while the input signal is at the second voltage level (e.g., a logical xe2x80x9c0xe2x80x9d) and the signal on the output of the logical enable device (and the gate of the driving transistor) is also at the second voltage level (e.g., a logical xe2x80x9c0xe2x80x9d).
The invention can also provide at least one pull-down delay element between the logical NAND device and the pull-down transistor and at least one pull-up delay element between the logical NOR device and the pull-up transistor. The pull-down delay element is connected in parallel with the signal line running between the logical NAND device and the pull-down transistor. The pull-up delay element is similarly connected in parallel with the signal line running between the logical NOR device and the pull-up transistor. This parallel arrangement provides that the delays created by the pull-down delay element and the pull-up delay element are dynamically varied depending upon the difference between the voltage level at the input to the logical enable device and the voltage level at the gate of the driving transistor.
If the pull-down transistor comprises a P-type transistor, it is directly connected to the logical NAND device. Similarly, if the pull-up transistor comprises an N-type transistor, it is also directly connected to the logical NOR device. Otherwise, if the pull-down transistor comprises an N-type transistor, the circuit further includes an inverter positioned between the logical NAND device and the pull-up transistor. Similarly, if the pull-up transistor comprises a P-type transistor, the circuit further includes an inverter positioned between the logical NOR device and the pull-up transistor.